Double data rate (DDR) memory links use burst-mode signaling, which means that data is transmitted in bursts of several bytes and in between these transmission bursts the transmitter is either in termination mode for the reception of data from the DRAM or in idle mode, the latter providing a high impedance state. DDR links are operated source-synchronously with unidirectional clocks and bidirectional data buses that are operated in half-duplex mode.
Intersymbol Interference (ISI) is a major source of jitter for high-speed serial links. There are a number of equalizer types known that may be applied to both transmitters and receivers of such links to reduce or eliminate the effect of ISI. Among these equalizers, decision feedback equalizers (DFEs) are widely-used discrete-time equalizers. A decision feedback equalizer stores and feeds back the decisions it has made for the previous bits and subtracts the ISI of these stored bits from the current signal.
Up to the DDR-4 standard, DFEs have not been used in DDR receivers because the data rate dependent eye closure due to ISI has been too little for the justification of a DFE and older standards such as DDR-4 through DDR-2 did not provide any DFE support in their transmission protocols. With the increase of data rate from 3.2 Gb/s for DDR-4 to 6.4 Gb/s for DDR-5, DFEs have now become part of the JEDEC standard for DRAM suppliers.
Hence there is a need for advantageous decision feedback equalizer circuits.